\doxysection{C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+STM32\+H7xx\+\_\+\+HAL\+\_\+\+Driver/\+Inc/stm32h7xx\+\_\+hal\+\_\+uart\+\_\+ex.h File Reference}
\hypertarget{stm32h7xx__hal__uart__ex_8h}{}\label{stm32h7xx__hal__uart__ex_8h}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_uart\_ex.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_uart\_ex.h}}


Header file of UART HAL Extended module.  


{\ttfamily \#include "{}stm32h7xx\+\_\+hal\+\_\+def.\+h"{}}\newline
\doxysubsubsection*{Classes}
\begin{DoxyCompactItemize}
\item 
struct \mbox{\hyperlink{struct_u_a_r_t___wake_up_type_def}{UART\+\_\+\+Wake\+Up\+Type\+Def}}
\begin{DoxyCompactList}\small\item\em UART wake up from stop mode parameters. \end{DoxyCompactList}\end{DoxyCompactItemize}
\doxysubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___word___length_gadaec9a23646032a333a5327d66aae4fe}{UART\+\_\+\+WORDLENGTH\+\_\+7B}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae19a4c9577dfb1569cf6f564fe6c4949}{USART\+\_\+\+CR1\+\_\+\+M1}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___word___length_gaf394e9abaf17932ee89591f990fe6407}{UART\+\_\+\+WORDLENGTH\+\_\+8B}}~0x00000000U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___word___length_gaf867be43de35fd3c32fe0b4dd4058f7e}{UART\+\_\+\+WORDLENGTH\+\_\+9B}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaf15ab248c1ff14e344bf95a494c3ad8}{USART\+\_\+\+CR1\+\_\+\+M0}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___wake_up___address___length_ga6599292020c484faeea894307d9dc6d5}{UART\+\_\+\+ADDRESS\+\_\+\+DETECT\+\_\+4B}}~0x00000000U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___wake_up___address___length_ga4dbd5995e0e4998cb1a312c183d7cbb0}{UART\+\_\+\+ADDRESS\+\_\+\+DETECT\+\_\+7B}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga2d8588feb26d8b36054a060d6b691823}{USART\+\_\+\+CR2\+\_\+\+ADDM7}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___f_i_f_o__mode_gaf55427ab3ae02f380954508d80b6dea3}{UART\+\_\+\+FIFOMODE\+\_\+\+DISABLE}}~0x00000000U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___f_i_f_o__mode_ga3ff44f476a9c4d0e6c98e50f513f3561}{UART\+\_\+\+FIFOMODE\+\_\+\+ENABLE}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gafb5e9fc4111b0159c65811f6a206c192}{USART\+\_\+\+CR1\+\_\+\+FIFOEN}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_gac0167b844b8cc2d183b55a0b296b2803}{UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+8}}~0x00000000U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga7b6a3451b4d3677ba49f05228832edad}{UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+4}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3cc91bacf5659188d4ef8d13fc48b5c3}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+0}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga3ded7de796281c47106eab832068534d}{UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+2}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4651a05997c8bef8485185f7c8874142}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+1}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga0dd7780c824caddd1476cb59b9d5e5d0}{UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+3\+\_\+4}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3cc91bacf5659188d4ef8d13fc48b5c3}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+0}}\texorpdfstring{$\vert$}{|}\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4651a05997c8bef8485185f7c8874142}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+1}})
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga8e36c5786a037adae9a124a3094fc374}{UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+7\+\_\+8}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa2683f01784119560144bd0c7fd8d85e}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+2}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level_ga302d541c0419d26567cc0da09486e73d}{UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD\+\_\+8\+\_\+8}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa2683f01784119560144bd0c7fd8d85e}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+2}}\texorpdfstring{$\vert$}{|}\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3cc91bacf5659188d4ef8d13fc48b5c3}{USART\+\_\+\+CR3\+\_\+\+TXFTCFG\+\_\+0}})
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_ga9cabde9885fe477df3625fa8fdc7a99a}{UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+8}}~0x00000000U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_ga46898e3dbaa13a52a62ae7dbddc90cd5}{UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+4}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf8b113e8d794dc256745b970cc2e4704}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+0}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_ga032d8a09e993ca8938eb6fa5b97f4d16}{UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+2}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga216b1b9afd21e8e4ba132605aacf7534}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+1}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_ga822019dbcf489602fe72d84700655e27}{UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+3\+\_\+4}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf8b113e8d794dc256745b970cc2e4704}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+0}}\texorpdfstring{$\vert$}{|}\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga216b1b9afd21e8e4ba132605aacf7534}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+1}})
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_gaba2b8f47d6b307a644ec4dcd6d8202e4}{UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+7\+\_\+8}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga24cb2175b76382753462bed1d36d518c}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+2}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_gabc5dc474eeac764ab6e99435ace5ca21}{UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+8\+\_\+8}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga24cb2175b76382753462bed1d36d518c}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+2}}\texorpdfstring{$\vert$}{|}\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf8b113e8d794dc256745b970cc2e4704}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+0}})
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___private___macros_ga2d8ffd4cb12754846ace609dff92e8df}{UART\+\_\+\+GETCLOCKSOURCE}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+,  \+\_\+\+\_\+\+CLOCKSOURCE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Report the UART clock source. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___private___macros_gad9330184a8bd9399a36bcc93215a50d1}{UART\+\_\+\+MASK\+\_\+\+COMPUTATION}}(\+\_\+\+\_\+\+HANDLE\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___private___macros_gaf856254e5a61d2ee81086918bffabde5}{IS\+\_\+\+UART\+\_\+\+WORD\+\_\+\+LENGTH}}(\+\_\+\+\_\+\+LENGTH\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Ensure that UART frame length is valid. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___private___macros_gaa4cf2a15ad7ae46e2905debeef35a908}{IS\+\_\+\+UART\+\_\+\+ADDRESSLENGTH\+\_\+\+DETECT}}(\+\_\+\+\_\+\+ADDRESS\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Ensure that UART wake-\/up address length is valid. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___private___macros_ga59f192f936bea1dac321a552ab3e662d}{IS\+\_\+\+UART\+\_\+\+TXFIFO\+\_\+\+THRESHOLD}}(\+\_\+\+\_\+\+THRESHOLD\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Ensure that UART TXFIFO threshold level is valid. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___private___macros_gac6cc8376326d3982bda0685dbaaff687}{IS\+\_\+\+UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD}}(\+\_\+\+\_\+\+THRESHOLD\+\_\+\+\_\+)
\begin{DoxyCompactList}\small\item\em Ensure that UART RXFIFO threshold level is valid. \end{DoxyCompactList}\end{DoxyCompactItemize}
\doxysubsubsection*{Functions}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+RS485\+Ex\+\_\+\+Init} (\mbox{\hyperlink{group___u_a_r_t___exported___types_ga5de4a49eb132735325e706f406c69d6e}{UART\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}huart, uint32\+\_\+t Polarity, uint32\+\_\+t Assertion\+Time, uint32\+\_\+t Deassertion\+Time)
\item 
void {\bfseries HAL\+\_\+\+UARTEx\+\_\+\+Wakeup\+Callback} (\mbox{\hyperlink{group___u_a_r_t___exported___types_ga5de4a49eb132735325e706f406c69d6e}{UART\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}huart)
\item 
void {\bfseries HAL\+\_\+\+UARTEx\+\_\+\+Rx\+Fifo\+Full\+Callback} (\mbox{\hyperlink{group___u_a_r_t___exported___types_ga5de4a49eb132735325e706f406c69d6e}{UART\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}huart)
\item 
void {\bfseries HAL\+\_\+\+UARTEx\+\_\+\+Tx\+Fifo\+Empty\+Callback} (\mbox{\hyperlink{group___u_a_r_t___exported___types_ga5de4a49eb132735325e706f406c69d6e}{UART\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}huart)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+UARTEx\+\_\+\+Stop\+Mode\+Wake\+Up\+Source\+Config} (\mbox{\hyperlink{group___u_a_r_t___exported___types_ga5de4a49eb132735325e706f406c69d6e}{UART\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}huart, \mbox{\hyperlink{struct_u_a_r_t___wake_up_type_def}{UART\+\_\+\+Wake\+Up\+Type\+Def}} Wake\+Up\+Selection)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+UARTEx\+\_\+\+Enable\+Stop\+Mode} (\mbox{\hyperlink{group___u_a_r_t___exported___types_ga5de4a49eb132735325e706f406c69d6e}{UART\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}huart)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+UARTEx\+\_\+\+Disable\+Stop\+Mode} (\mbox{\hyperlink{group___u_a_r_t___exported___types_ga5de4a49eb132735325e706f406c69d6e}{UART\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}huart)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+Multi\+Processor\+Ex\+\_\+\+Address\+Length\+\_\+\+Set} (\mbox{\hyperlink{group___u_a_r_t___exported___types_ga5de4a49eb132735325e706f406c69d6e}{UART\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}huart, uint32\+\_\+t Address\+Length)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+UARTEx\+\_\+\+Enable\+Fifo\+Mode} (\mbox{\hyperlink{group___u_a_r_t___exported___types_ga5de4a49eb132735325e706f406c69d6e}{UART\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}huart)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+UARTEx\+\_\+\+Disable\+Fifo\+Mode} (\mbox{\hyperlink{group___u_a_r_t___exported___types_ga5de4a49eb132735325e706f406c69d6e}{UART\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}huart)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+UARTEx\+\_\+\+Set\+Tx\+Fifo\+Threshold} (\mbox{\hyperlink{group___u_a_r_t___exported___types_ga5de4a49eb132735325e706f406c69d6e}{UART\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}huart, uint32\+\_\+t Threshold)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+UARTEx\+\_\+\+Set\+Rx\+Fifo\+Threshold} (\mbox{\hyperlink{group___u_a_r_t___exported___types_ga5de4a49eb132735325e706f406c69d6e}{UART\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}huart, uint32\+\_\+t Threshold)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+UARTEx\+\_\+\+Receive\+To\+Idle} (\mbox{\hyperlink{group___u_a_r_t___exported___types_ga5de4a49eb132735325e706f406c69d6e}{UART\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}huart, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size, uint16\+\_\+t \texorpdfstring{$\ast$}{*}Rx\+Len, uint32\+\_\+t Timeout)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+UARTEx\+\_\+\+Receive\+To\+Idle\+\_\+\+IT} (\mbox{\hyperlink{group___u_a_r_t___exported___types_ga5de4a49eb132735325e706f406c69d6e}{UART\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}huart, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\+\_\+\+Status\+Type\+Def}} {\bfseries HAL\+\_\+\+UARTEx\+\_\+\+Receive\+To\+Idle\+\_\+\+DMA} (\mbox{\hyperlink{group___u_a_r_t___exported___types_ga5de4a49eb132735325e706f406c69d6e}{UART\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}huart, uint8\+\_\+t \texorpdfstring{$\ast$}{*}p\+Data, uint16\+\_\+t Size)
\item 
\mbox{\hyperlink{group___u_a_r_t___exported___types_gadddf3d5480235c945dc8eec58f961203}{HAL\+\_\+\+UART\+\_\+\+Rx\+Event\+Type\+Type\+Def}} {\bfseries HAL\+\_\+\+UARTEx\+\_\+\+Get\+Rx\+Event\+Type} (const \mbox{\hyperlink{group___u_a_r_t___exported___types_ga5de4a49eb132735325e706f406c69d6e}{UART\+\_\+\+Handle\+Type\+Def}} \texorpdfstring{$\ast$}{*}huart)
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Header file of UART HAL Extended module. 

\begin{DoxyAuthor}{Author}
MCD Application Team 
\end{DoxyAuthor}
\begin{DoxyAttention}{Attention}

\end{DoxyAttention}
Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-\/\+IS. 